agilent AMMC-6120 8-20 ghz output x2 active frequency multiplier data sheet features input frequency range: 4-10 ghz broad input power range: -3 to +6 dbm output power: +14 dbm (pin = +2 dbm) fundamental suppression of 25 dbc 50 ? input and output match supply bias of -1.2 v, 4.5 v and 85 ma applications microwave radio systems satellite vsat, dbs up/down link lmds & pt-pt mmw long haul broadband wireless access (including 802.16 and 802.20 wimax) wll and mmds loops commercial grade military description agilents AMMC-6120 is an easy- to-use x2 active frequency multiplier mmic designed for commercial communication systems. though capable of doubling to 24 ghz with reduced fundamental suppression, the mmic is designed to take a 4 to 10 ghz input and double it to 8 to 20 ghz. it has integrated output amplifier, matching harmonic suppression, and bias networks. the input/output are matched to 50 ? and fully dc blocked. the mmic is fabricated using phemt technology. the backside of this die is both rf and dc ground. AMMC-6120 absolute maximum ratings [1] symbol parameters/conditions units min. max. v d positive drain voltage v 7 v g gate supply voltage v -3.0 0.5 i d drain current ma 120 p in cw input power dbm 15 t ch operating channel temp. c +150 t stg storage case temp. c -65 +150 t max maximum assembly temp. c +300 (60 sec. max.) note: 1. operation in excess of any one of these conditions may result in permanent damage to this device. this helps simplify the assembly process and reduces assembly related performance variations and costs. this mmic is a cost effective alternative to bulky hybrid fet and diode doublers that require high input drive power, have high c.l. and poor fundamental suppression. chip size: 1600 x 1000 m (64 x 40 mils) chip size tolerance: 10 m ( 0.4 mils) chip thickness: 100 10 m (4 0.4 mils) pad dimensions: 120 x 80 m (5x3 0.4 mils) attention: observe precautions for handling electrostatic sensitive devices. esd machine model (class a) esd human body model (class 0) refer to agilent application note a004r: electrostatic discharge damage and control.
2 AMMC-6120 dc specifications/physical properties [1] symbol parameters and test conditions units min. typ. max. i d drain supply current (under any ma 80 85 105 rf power drive and temperature) (v d = 4.5 v) v g gate supply operating voltage v -1.5 -1.2 -1.0 q ch-b thermal resistance [2] (backside temperature, t b = 25 c) c/w 25 notes: 1. ambient operational temperature t a = 25 c unless otherwise noted. 2. channel-to-backside thermal resistance ( q ch-b ) = 26 c/w at t channel (t c ) = 34 c as measured using infrared microscopy. thermal resistance at backside temperature (t b ) = 25 c calculated from measured data. AMMC-6120 rf specifications [3,4,5] t a = 25 c, v d = 4.5 v, i d(q) = 85 ma, z o = 50 ? symbol parameters and test conditions units minimum typical maximum sigma fin input frequency ghz 4 to 10 fout output frequency ghz 8 to 20 po output power [4] dbm 11.5 14 0.6 fo fundamental isolation dbc 18 25 1.8 (referenced to po) 3fo 3 rd harmonic isolation dbc 25 2.5 (referenced to po) p -1db input power at 1db gain compression dbm +1 rlin input return loss [6] db -15 rlout output return loss [6] db -9 ssb single sideband phase noise dbc/hz -135 (100 khz offset) notes: 3. small/large -signal data measured in wafer form t a = 25 c. 4. 100% on-wafer rf test is done at pin = +2 dbm, output frequency = 9, 16, and 20 ghz. 5. specifications are derived from measurements in a 50- w test environment. aspects of the multiplier performance may be improved over a more narrow bandwidth by application of additional matching. 2fo pout (dbm) @ 20-ghz 3fo-suppression(dbc) @ 30-ghz fo-suppression (dbc) @ 10-ghz typical distribution of pout, 2 nd -harmonic & 3 rd -harmonic suppression (fin = 10 ghz, pin = 0 dbm). based on 1800 parts sampled over several production lots. 13 14 15 19 21 23 25 27 29 31 33 35 20 30
3 figure 1. typical output power against fundamental, 3 rd , and 4 th harmonic suppression (p in = +2 dbm) vs. frequency. AMMC-6120 typical performances (t a = 25 c, v d = 4.5 v, i d = 85 ma, v g = -1.2 v, z in = z out = 50 w unless otherwise stated) note: these measurements are in 50 w test environment. aspects of the amplifier performance may be improved over a narrower bandwidth by application of additional conjugate, linearity or low noise ( g opt) matching. figure 2. typical output power at different fundamental input power vs. frequency. figure 3. typical input and output return loss. figure 4. typical output power against fundamental, 3 rd , and 4 th harmonic suppression vs. p in (2h = 10 ghz). figure 5. typical output power against fundamental, 3 rd , and 4 th harmonic suppression vs. p in (2h = 12 ghz). figure 6. typical output power against fundamental, 3 rd , and 4 th harmonic suppression vs. p in (2h = 22 ghz). figure 7. typical output power and fundamental suppression vs. temperature. figure 8. typical output power and fundamental suppresion vs. vd. figure 9. typical pout and fundamental suppression vs. vg (fout = 16 ghz). 20 10 -40 -11 -5 3 5 7 9 11 p in (dbm) pout (dbm) 0 -9 -7 -3 -1 -20 -30 -10 1 2h = 10 ghz 3h 4h fundamental 20 10 -40 -11 -5 3 5 7 9 11 p in (dbm) pout (dbm) 0 -9 -7 -3 -1 -20 -30 -10 1 2h = 12 ghz 3h 4h fundamental 20 10 -40 -11 -5 3 5 7 9 11 p in (dbm) pout (dbm) 0 -9 -7 -3 -1 -20 -30 -10 1 2h = 22 ghz 3h 4h fundamental 20 10 15 0 -20 -35 -30 812 18202224 output frequency (ghz) pout (dbm) 5 10 14 -15 -25 -5 -10 16 2h (@ -40 c) 2h (@ +25 c) 2h (@ +85 c) 1h (@ -40 c) 1h (@ +25 c) 1h (@ +85 c) 20 10 15 0 -20 -35 -30 812 18202224 output frequency (ghz) pout (dbm) 5 10 14 -15 -25 -5 -10 16 2h (@vd = 4.0 v) 2h (@vd = 4.5 v) 2h (@vd = 5.0 v) 1h (@vd = 4.0 v) 1h (@vd = 4.5 v) 1h (@vd = 5.0 v) 20 10 15 0 -20 -30 pout (dbm) 5 -15 -25 -5 -10 2h (@vg = -1.0 v) 2h (@vg = -1.2 v) 2h (@vg = -1.4 v) 1h (@vg = -1.0 v) 1h (@vg = -1.2 v) 1h (@vg = -1.4 v) -11 -5 3 5 7 9 11 p in (dbm) -9 -7 -3 -1 1 0 -5 -30 2182226 frequency (ghz) input output s11 & s22 (db) -10 610 -20 -25 -15 14 s11 s22 20 10 15 0 -20 -30 812 18202224 output frequency (ghz) pout (dbm) 5 10 14 -15 -25 -5 -10 16 o/p freq. = 2*fin fundamental 3h 4h 16 14 15 12 8 6 812 18202224 output frequency (ghz) pout (dbm) 13 10 14 9 7 11 10 16 pin = 0 dbm pin = +2 dbm pin = +4 dbm pin = +6 dbm
4 biasing and operation the frequency doubler mmic consists of a differential amplifier circuit that acts as an active balun. the outputs of this balun feed the gates of balanced fets and the drains are connected to form the single-ended output. this results in the fundamental frequency and odd harmonics canceling and the even harmonic drain currents (in phase) adding in superposition. node s acts as a virtual ground. an input matching network (m/n) is designed to provide good match at fundamental frequencies and produces high impedance mismatch at higher harmonics. AMMC-6120 is biased with a single positive drain supply and single negative gate supply using separate bypass capacitors. it is normally biased with the drain supply connected to both the vdab and the vdd bond pads and the gate supply connected to the vgd bond pad. it is important to bypass both vdab and vdd with 100 pf capacitors placed as close to the die as possible. typical bias connections are shown in figure 12. for most of the application it is recommended to use a vg = C1.2 v and vd = 4.5 v. the AMMC-6120 performance changes very slightly with drain (vd) and gate bias (vg) as shown in figure 8 and 9. minor improve- ments in performance are possible for output power or fundamental suppression by optimizing the vg from C1.0 v to C1.4 v and/or vd from 4.0 to 5.0 v. the rf input and output port are ac coupled thus no dc voltage is present at either ports. however, the rf output port has a internal output-matching circuit that presents a dc short. proper care should be taken while biasing sequential circuit to AMMC-6120 as it might cause dc short (use a dc block if sub sequential circuit is not ac coupled). no ground wires are needed since ground connections are made with plated through-holes to the backside of the device. refer the absolute maximum ratings table for allowed dc and thermal conditions. assembly techniques the backside of the mmic chip is rf ground. for microstrip applications the chip should be attached directly to the ground plane (e.g. circuit carrier or heatsink) using electrically conductive epoxy [1] . for best performance, the topside of the mmic should be brought up to the same height as the circuit surrounding it. this can be accomplished by mounting a gold plate metal shim (same length and width as the mmic) under the chip which is of correct thickness to make the chip and adjacent circuit the same height. the amount of epoxy used for the chip and/or shim attachment should be just enough to provide a thin fillet around the bottom perimeter of the chip or shim. the ground plan should be free of any residue that may jeopardize electrical or mechanical attachment. the location of the rf bond pads is shown in figure 11. note that all the rf input and output ports are in a ground-signal-ground configuration. rf connections should be kept as short as reasonable to minimize performance degradation due to undesirable series inductance. a single bond wire is normally sufficient for signal connections, however double bonding with 0.7 mil gold wire or use of gold mesh [2] is recommended for best performance, especially near the high end of the frequency band. thermosonic wedge bonding is the preferred method for wire attachment to the bond pads. gold mesh can be attached using a 2 mil round tracking tool and a tool force of approximately 22 grams and a ultrasonic power of roughly 55 db for a duration of 76 8 ms. the guided wedge at an ultrasonic power level of 64 db can be used for 0.7 mil wire. the recommended wire bond stage temperature is 150 2 c. caution should be taken to not exceed the absolute maximum rating for assembly temperature and time. the chip is 100 m thick and should be handled with care. this mmic has exposed air bridges on the top surface and should be handled by the edges or with a custom collet (do not pick up the die with a vacuum on die center). this mmic is also static sensitive and esd precautions should be taken. notes: 1.ablebond 84-1 lm1 silver epoxy is recommended. 2.buckbee-mears corporation, st. paul, mn, 800-262-3824 m/n @ fo m/n @ 2fo s a. diff. amp active balun
5 figure 10. AMMC-6120 simplified schematic. figure 11. AMMC-6120 bonding pad locations. figure 12. AMMC-6120 assembly diagram. rfin rfout vdab vgd vdd 1000 715 0 1600 0 0 660 rfin vdab 660 rfi 472 rfout 1310 vgd 1478 vdd vd /100 pf /100 pf vg vdab vgd vdd rfout rfin 50 ohm line 50 ohm line
www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152 (domestic/interna- tional), or 0120-61-1280 (domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2005 agilent technologies, inc. february 18, 2005 5989-2290en ordering information: AMMC-6120-w10 = 10 devices per tray AMMC-6120-w50 = 50 devices per tray
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